VHDL - 예약어, 연산자 요약
□ VHDL 예약어와 연산자 ○ 예약어 abs, access, after, alias, all, and, architecture, array, assert, attribute, begin, block, body, buffer, bus, case, component, configuration, constant, disconnect, downto, else, elseif, end, entity, exit, file, for, function, generate, generic, guarded, if, in, inout, is, label, library, linkage, loop, map, mod, nand, new, nor, not, null, of, on, open, or, others, out, pack..
